Lead Applications Engineer – DDR Design IP
Job title: Lead Applications Engineer – DDR Design IP
Company: Cadence Design Systems
Job description: and designers · Write application notes, user guides, articles, design ideas, new product proposals, and evaluation kit… on memory subsystem verification and/or performance analysis · Knowledge of System Verilog and FPGA design · Knowledge…
Expected salary: $102900 – 191100 per year
Location: San Jose, CA
Job date: Sun, 05 Oct 2025 02:36:11 GMT
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