Senior Applications Engineer – DDR Design IP
Job title: Senior Applications Engineer – DDR Design IP
Company: Cadence Design Systems
Job description: Applications Engineer – DDR Design IP Job Location: San Jose, CA Job Description The Cadence IP team develops industry leading… Experience on memory subsystem verification and/or performance analysis Strong knowledge of ASIC flow, RTL design in Verilog…
Expected salary: $84000 – 156000 per year
Location: San Jose, CA
Job date: Sun, 05 Oct 2025 05:41:16 GMT
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